/* verilator lint_off UNUSEDSIGNAL */
`include "defines.svh"
module identIMM(
    input word_t instr,
    input logic[2:0] imm_sel,
    output word_t imm
);
word_t immI,immU,immS,immB,immJ;
assign immI = {{20{instr[31]}}, instr[31:20]};
assign immU = {instr[31:12], 12'b0};
assign immS = {{20{instr[31]}}, instr[31:25], instr[11:7]};
assign immB = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
assign immJ = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};

always_comb begin
    case(imm_sel)
        3'b000: imm = immI;
        3'b001: imm = immU;
        3'b010: imm = immS;
        3'b011: imm = immB;
        3'b100: imm = immJ;
        default: imm = 32'b0;
    endcase
end

endmodule
